/*-------------------------------------------------------------------------- TOUCHCORE10.H (ver 0.1) Header file for the GenCore Turbo TOUCHCORE10 Series TOUCHCORE10-QF20IP : 20 Pins QFP Package TOUCHCORE10-SO20IP : 20 Pins SOIC Package TOUCHCORE10-SO8IP : 8 Pins SOIC Package Copyright (c) 2003-2008 CORERIVER Semiconductor. All rights reserved. --------------------------------------------------------------------------*/ #ifndef TC10_HEADER_FILE #define TC10_HEADER_FILE 1 /*------------------------------------------------ Byte Registers ------------------------------------------------*/ sfr P0 = 0x80; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr ITSEL = 0x86; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr P1 = 0x90; sfr EXIF = 0x91; sfr CLKOFF = 0x94; sfr RINGCON = 0x95; sfr SCON = 0x98; sfr SBUF = 0x99; sfr TSCHEN = 0x9A; sfr TSRDIV = 0x9B; sfr TSCNT0 = 0x9C; sfr TSCNT1 = 0x9D; sfr TSCNT2 = 0x9E; sfr TSCNT3 = 0x9F; sfr P2 = 0xA0; sfr TSCLK = 0xA1; sfr TSOFFL = 0xA3; sfr TSCNT4 = 0xA4; sfr TSCNT5 = 0xA5; sfr TSCNT6 = 0xA6; sfr TSCNT7 = 0xA7; sfr IE = 0xA8; sfr TSCON = 0xA9; sfr TSCFG = 0xAA; sfr TSOFFH = 0xAB; sfr I2CST0 = 0xB0; sfr I2CCON0 = 0xB3; sfr I2CCFG0 = 0xB4; sfr I2CSLA0 = 0xB5; sfr I2CDAT0 = 0xB6; sfr I2CSCL0 = 0xB7; sfr IP = 0xB8; sfr OSCICN = 0xBE; sfr OSC2ICN = 0xBF; sfr PMR = 0xC4; sfr STATUS = 0xC5; sfr I2CST1 = 0xC8; sfr I2CCON1 = 0xCB; sfr I2CCFG1 = 0xCC; sfr I2CSLA1 = 0xCD; sfr I2CDAT1 = 0xCE; sfr PSW = 0xD0; sfr WDMOD = 0xD1; sfr P0TYPE = 0xD4; sfr P1TYPE = 0xD5; sfr P2TYPE = 0xD6; sfr WDCON = 0xD8; sfr ADCHL = 0xD9; sfr ADCHSEL = 0xDB; sfr PWMCON = 0xDC; sfr PWMIF = 0xDD; sfr PWMD = 0xDE; sfr ACC = 0xE0; sfr ADCSELH = 0xE1; sfr ADCSEL = 0xE2; sfr ALTSEL = 0xE3; sfr P0SEL = 0xE4; sfr P1SEL = 0xE5; sfr P2SEL = 0xE6; sfr EIE = 0xE8; sfr ADCR = 0xEE; sfr ADCON = 0xEF; sfr B = 0xF0; sfr P0DIR = 0xF4; sfr P1DIR = 0xF5; sfr P2DIR = 0xF6; sfr EIP = 0xF8; sfr EECNTLD = 0xF9; sfr EECNTL = 0xFA; sfr EECNTM = 0xFB; sfr EECNTH = 0xFC; sfr EEAEN = 0xFF; /*------------------------------------------------ I2CST Bit Register ------------------------------------------------*/ sbit I2CBF = 0xB0; sbit I2CS = 0xB1; sbit I2CP = 0xB2; sbit I2CDA = 0xB3; sbit I2CRW = 0xB4; sbit I2CACK = 0xB5; sbit I2COF = 0xB6; sbit I2CIF = 0xB7; /*------------------------------------------------ I2CST1 Bit Register ------------------------------------------------*/ sbit I2CBF1 =0xC8; sbit I2CS1 = 0xC9; sbit I2CP1 = 0xCA; sbit I2CDA1 = 0xCB; sbit I2CRW1 = 0xCC; sbit I2CACK1 = 0xCD; sbit I2COF1 = 0xCE; sbit I2CIF1 = 0xCF; /*------------------------------------------------ P0 Bit Register ------------------------------------------------*/ sbit P0_0 = 0x80; sbit P0_1 = 0x81; sbit P0_2 = 0x82; sbit P0_3 = 0x83; sbit P0_4 = 0x84; sbit P0_5 = 0x85; sbit P0_6 = 0x86; sbit P0_7 = 0x87; sbit P00 = 0x80; sbit P01 = 0x81; sbit P02 = 0x82; sbit P03 = 0x83; sbit P04 = 0x84; sbit P05 = 0x85; sbit P06 = 0x86; sbit P07 = 0x87; sbit INT0 = 0x80; sbit PWM = 0x80; sbit TVO = 0x80; sbit INT1 = 0x81; sbit RXD = 0x81; sbit INT2 = 0x82; sbit TXD = 0x82; sbit INT3 = 0x83; /*------------------------------------------------ PCON Bit Values ------------------------------------------------*/ #define IDL_ 0x01 /* IDLE Mode Bit */ #define PD_ 0x02 /* Power Down Mode Bit */ #define STOP_ 0x02 /* Alternate definition */ #define GF0_ 0x04 /* General Purpose Flag */ #define GF1_ 0x08 /* General Purpose Flag */ #define POF_ 0x10 /* Power Off Flag */ #define SMOD0_ 0x40 /* When Set, FE Bis Access Enable */ /*------------------------------------------------ TCON Bit Register ------------------------------------------------*/ sbit IT0 = 0x88; sbit IE0 = 0x89; sbit IT1 = 0x8A; sbit IE1 = 0x8B; sbit TR0 = 0x8C; sbit TF0 = 0x8D; sbit TR1 = 0x8E; sbit TF1 = 0x8F; /*------------------------------------------------ TMOD Bit Values ------------------------------------------------*/ #define T0_M0_ 0x01 /* T0_M1, T0_M0 : Timer 0 Mode Select. */ #define T0_M1_ 0x02 #define T0_CT_ 0x04 /* Timer 0 Counter/Timer Select. When Set, COunter by T0 pin. */ #define T0_GATE_ 0x08 /* Timer 0 Gate Control */ #define T0_MASK_ 0x0F /*------------------------------------------------ P1 Bit Register ------------------------------------------------*/ sbit P1_0 = 0x90; sbit P1_1 = 0x91; sbit P1_2 = 0x92; sbit P1_3 = 0x93; sbit P1_4 = 0x94; sbit P1_5 = 0x95; sbit P1_6 = 0x96; sbit P1_7 = 0x97; sbit P10 = 0x90; sbit P11 = 0x91; sbit P12 = 0x92; sbit P13 = 0x93; sbit P14 = 0x94; sbit P15 = 0x95; sbit P16 = 0x96; sbit P17 = 0x97; /*------------------------------------------------ EXIF Bit Value ------------------------------------------------*/ #define BGS_ 0x01 /* Band-gap Select. When set, LVD will run in power-down mode. */ #define RGSL_ 0x02 /* When wakeup from power down mode in XTAL clock, use RING oscillator as system clock during 65,536 XTAL clocks */ #define RGMD_ 0x04 /* RING mode */ #define XTRG_ 0x08 /* Crystal Select. Read only*/ #define IE2_ 0x10 /* External Interrupt 2 Flag */ #define IE3_ 0x20 /* External Interrupt 3 Flag_b */ #define RTRG_ 0x40 #define XTRG2_ 0x80 /*------------------------------------------------ SCON Bit Register ------------------------------------------------*/ sbit RI = 0x98; sbit TI = 0x99; sbit REN = 0x9C; /*------------------------------------------------ P2 Bit Register ------------------------------------------------*/ sbit P2_0 = 0xA0; sbit P2_1 = 0xA1; sbit P2_2 = 0xA2; sbit P2_3 = 0xA3; sbit P2_4 = 0xA4; sbit P2_5 = 0xA5; sbit P2_6 = 0xA6; sbit P2_7 = 0xA7; sbit P20 = 0xA0; sbit P21 = 0xA1; sbit P22 = 0xA2; sbit P23 = 0xA3; sbit P24 = 0xA4; sbit P25 = 0xA5; sbit P26 = 0xA6; sbit P27 = 0xA7; sbit T0 = 0xA0; /*------------------------------------------------ IE Bit Register ------------------------------------------------*/ sbit EX0 = 0xA8; sbit ET0 = 0xA9; sbit EX1 = 0xAA; sbit ET1 = 0xAB; sbit ES = 0xAC; sbit ET2 = 0xAD; sbit EADC = 0xAE; sbit EA = 0xAF; /*------------------------------------------------ IP Bit Register ------------------------------------------------*/ sbit PX0 = 0xB8; sbit PT0 = 0xB9; sbit PX1 = 0xBA; sbit PT1 = 0xBB; sbit PS = 0xBC; sbit PT2 = 0xBD; sbit PADC = 0xBE; /*------------------------------------------------ OSCIN (BEh) Bit Value ------------------------------------------------*/ #define DIV0_ 0x01 /* DIV[2:0] : Ring Oscillator Divider */ #define DIV1_ 0x02 #define DIV2_ 0x08 /* [0,0,0] = 4MHz (Default) [0,0,1] = 2MHz [0,1,0] = 1MHz [0,1,1] = 0.5MHz [1,0,0] = 24MHz [1,0,1] = 12MHz [1,1,0] = 6MHz [1,1,1] = 3MHz */ #define RINGON_ 0x04 /* 1 = RINGON : Internal Ring Osc. is running. (Default) 0 = RINGON : Internal Ring Osc. is killed. Don't clear RINGON when XTRG = 1 (Sys CLK = Crystal Osc). */ /*------------------------------------------------ TSRDIV (9Bh) Bit Value ------------------------------------------------*/ #define TSRDIV0_ 0x01 /* TSRDIV[2:0] : Touch Sensor RING Oscillator Divider */ #define TSRDIV1_ 0x02 #define TSRDIV2_ 0x04 /* [0,0,0] = 0.5MHz (Default) [0,0,1] = 1MHz [0,1,0] = 2MHz [0,1,1] = 3MHz [1,0,0] = 4MHz [1,0,1] = 6MHz [1,1,0] = 12MHz [1,1,1] = 24MHz /*------------------------------------------------ TSCLK (A1h) Bit Value ------------------------------------------------*/ #define TSRCK0_ 0x01 /* TSRCK[3:0] : Touch Sensor Reference Clock Divider */ #define TSRCK1_ 0x02 /* F_TSR = Fsys/(2^(1+TSRCK[3:0])) */ #define TSRCK2_ 0x04 #define TSRCK3_ 0x08 #define TSRCK_CLR_ 0xF0 #define TSSCK0_ 0x10 /* TSSCK[2:0] : Touch Sensor Sampling Clock Divider */ #define TSSCK1_ 0x20 /* F_TSS = F_TS/(2^(TSSCK[2:0])) */ #define TSSCK2_ 0x40 #define TSSCK_CLR_ 0x0F /*------------------------------------------------ TSCON (A9h) Bit Value ------------------------------------------------*/ #define TSIF_CLR_ 0xFD #define TSIF_ 0x02 #define TS_RUN_ 0x01 /*------------------------------------------------ TSCFG (AAh) Bit Value ------------------------------------------------*/ #define TSOP_ 0x02 #define TSMOD_ 0x01 /*------------------------------------------------ PMR (C4h) Bit Value ------------------------------------------------*/ #define XTOFF_ 0x08 /* 0 = XTOFF : External Crystal Osc. is running. (Default) 1 = XTOFF : External Crystal Osc. is killed. Don't set XTOFF when XTRG = 1 (Sys CLK = Crystal Osc). */ /*------------------------------------------------ PSW Bit Register ------------------------------------------------*/ sbit P = 0xD0; sbit F1 = 0xD1; sbit OV = 0xD2; sbit RS0 = 0xD3; sbit RS1 = 0xD4; /* [1,0] : Bank 2, [1,1] = Bank 3 */ sbit F0 = 0xD5; sbit AC = 0xD6; sbit CY = 0xD7; /*------------------------------------------------ P0TYPE (D4h) Bit Value ------------------------------------------------*/ #define P0TY7_ 0x80 /* Port0 push-pull/open-drain control */ #define P0TY6_ 0x40 /* 0 = Push-pull (Default) */ #define P0TY5_ 0x20 /* 1 = Open-drain */ #define P0TY4_ 0x10 #define P0TY3_ 0x08 #define P0TY2_ 0x04 #define P0TY1_ 0x02 #define P0TY0_ 0x01 /*------------------------------------------------ P1TYPE (D5h) Bit Value ------------------------------------------------*/ #define P1TY7_ 0x80 /* Port1 push-pull/open-drain control */ #define P1TY6_ 0x40 /* 0 = Push-pull (Default) */ #define P1TY5_ 0x20 /* 1 = Open-drain */ #define P1TY4_ 0x10 #define P1TY3_ 0x08 #define P1TY2_ 0x04 #define P1TY1_ 0x02 #define P1TY0_ 0x01 /*------------------------------------------------ P2TYPE (D6h) Bit Value ------------------------------------------------*/ #define P2TY7_ 0x80 /* Port2 push-pull/open-drain control */ #define P2TY6_ 0x40 /* 0 = Push-pull (Default) */ #define P2TY5_ 0x20 /* 1 = Open-drain */ #define P2TY4_ 0x10 #define P2TY3_ 0x08 #define P2TY2_ 0x04 #define P2TY1_ 0x02 #define P2TY0_ 0x01 /*------------------------------------------------ WDCON Bit Register ------------------------------------------------*/ sbit RWT = 0xD8; sbit EWT = 0xD9; sbit WTRF = 0xDA; sbit WDIF = 0xDB; sbit PFI = 0xDC; sbit EPFI = 0xDD; sbit WD0 = 0xDE; sbit WD1 = 0xDF; /*------------------------------------------------ PWMCON (DCh) Bit Value ------------------------------------------------*/ #define RUN_P0_ 0x01 /* Counter Start Enable */ #define CLR_P0_ 0x02 /* Counter Reset Enable. Clear by H/W */ #define PWMF_ 0x04 /* PWM Interrupt Flag */ #define PS0_P_ 0x10 /* [PS2_P0, PS1_P0, PS0_P0] :*/ #define PS1_P_ 0x20 /* Prescaled Clock Selection */ #define PS2_P_ 0x40 /* [0,0,0] = Fosc, [0,0,1] = Fosc/2, [0,1,0] = Fosc/4, [0,1,1] = Fosc/8, [1,0,0] = Fosc/16, [1,0,1] = Fosc/32, [1,1,0] = Fosc/64, [1,1,1] = Fosc/128, */ #define P0SEL_ 0x80 /* PWM Output Enable to P0.6 */ /* How to Enable PWM Output ------------------------ [How to Enable PWM Output to P0.0] Refer to ALTSEL (E3h) Setting. 0 = PWM00 : PWM Output Disable to P0.0 (Default) 1 = PWM00 : PWM Output Enable to P0.0 [How to Enable PWM Output to P0.6] Refer to PWMCON (DCh) Setting. 0 = P0SEL : PWM Output Disable to P0.6 (Default) 1 = P0SEL : PWM Output Enable to P0.6 */ /*------------------------------------------------ ALTSEL (E3h) Bit Value ------------------------------------------------*/ #define TX_ 0x04 /* 1 = UART TX Data Output to P0.2 */ /* 0 = TX : as I/O(P0.2). (Default) */ #define TVO_ 0x08 /* 1 = Timer0 Overflow Clock to P0.0 */ /* 0 = TVO : as I/O(P0.8). (Default) */ #define PWM00_ 0x10 /* PWM Output Enable to P0.0 */ /* How to Enable PWM Output ------------------------ [How to Enable PWM Output to P0.0] Refer to ALTSEL (E3h) Setting. 0 = PWM00 : PWM Output Disable to P0.0 (Default) 1 = PWM00 : PWM Output Enable to P0.0 [How to Enable PWM Output to P0.6] Refer to PWMCON (DCh) Setting. 0 = P0SEL : PWM Output Disable to P0.6 (Default) 1 = P0SEL : PWM Output Enable to P0.6 */ #define CLO_ 0x20 /* 1 = CLO : System Clock Output to P2.6 */ /* 0 = CLO : as I/O(P2.6) (Default) */ #define IORSTEN_ 0x40 /* 1 = IORSTEN : RESETB -> as I/O(P1.2).*/ /* 0 = IORSTEN : RESETB Input (Default). */ #define IOXEN_ 0x80 /* 1 = IOXEN : XTAL1 & XTAL2 -> as I/Os(P1[1:0])*/ /* 0 = IOXEN : XTAL1 & XTAL2 Inputs (Default) */ /*------------------------------------------------ ADCHSEL (DBh) Bit Value ------------------------------------------------*/ // ADCH0~H15 : Default Flag = 1, Select = 0. #define ADCH0 0x80 /* 1 = ADCH0 in ADCHSEL. Port 1.2 */ #define ADCH1 0x81 /* 1 = ADCH1 in ADCHSEL. Port 1.3 */ #define ADCH2 0x82 /* 1 = ADCH2 in ADCHSEL. Port 2.0 */ #define ADCH3 0x83 /* 1 = ADCH3 in ADCHSEL. Port 2.1 */ #define ADCH4 0x84 /* 1 = ADCH4 in ADCHSEL. Port 2.7 */ #define ADCH5 0x85 /* 1 = ADCH5 in ADCHSEL. Port 1.4 */ #define ADCH6 0x86 /* 1 = ADCH6 in ADCHSEL. Port 1.5 */ #define ADCH7 0x87 /* 1 = ADCH7 in ADCHSEL. Port 1.6 */ #define ADCH8 0x88 /* 1 = ADCH8 in ADCHSEL. Port 1.7 */ #define ADCH9 0x89 /* 1 = ADCH9 in ADCHSEL. Port 0.0 */ #define ADCH10 0x8A /* 1 = ADCH10 in ADCHSEL. Port 3.0 */ #define ADCH11 0x8B /* 1 = ADCH11 in ADCHSEL. Port 3.1 */ #define ADCH12 0x8C /* 1 = ADCH12 in ADCHSEL. Port 3.2 */ #define ADCH13 0x8D /* 1 = ADCH13 in ADCHSEL. Port 3.3 */ #define ADCH14 0x8E /* 1 = ADCH14 in ADCHSEL. Port 3.4 */ #define ADCH15 0x8F /* 1 = ADCH15 in ADCHSEL. Port 3.5 */ /*------------------------------------------------ ADCSEL (E2h) Bit Value ------------------------------------------------*/ // Before setting the CH[3:0], clear CH[3:0] and then setting CH[3:0] #define CH0_ 0x01 /* CH[3:0] : ADC Channel Selector */ #define CH1_ 0x02 /* [0,0,0,0] = ADC0, [0,0,0,1] = ADC1, */ #define CH2_ 0x04 /* [0,0,1,0] = ADC2, [0,0,1,1] = ADC3, */ #define CH3_ 0x08 /* [0,1,0,0] = ADC4, [0,1,0,1] = ADC5, [0,1,1,0] = ADC6, [0,1,1,1] = ADC7, [1,0,0,0] = ADC8, [1,0,0,1] = ADC9, [1,0,1,0] = ADC10, or [1,0,1,1] = ADC11 is selected */ // ADC0B~11B : Default Flag = 1, Select = 0. #define ADC0B_ 0xEF /* 1 = ADC0B in ADCSEL(E2h). Port 0.1 */ #define ADC1B_ 0xDF /* 1 = ADC1B in ADCSEL. Port 0.2 */ #define ADC2B_ 0xBF /* 1 = ADC2B in ADCSEL. Port 0.3 */ #define ADC3B_ 0x7F /* 1 = ADC3B in ADCSEL. Port 0.4 */ /*------------------------------------------------ ADCSELH (E1h) Bit Value ------------------------------------------------*/ #define ADC4B_ 0xFE /* 1 = ADC4B in ADCSELH(E1h). Port 0.5 */ #define ADC5B_ 0xFD /* 1 = ADC5B in ADCSELH. Port 0.6 */ #define ADC6B_ 0xFB /* 1 = ADC6B in ADCSELH. Port 0.7 */ #define ADC7B_ 0xF7 /* 1 = ADC7B in ADCSELH. Port 2.6 */ #define ADC8B_ 0xEF /* 1 = ADC8B in ADCSELH. Port 2.5 */ #define ADC9B_ 0xDF /* 1 = ADC9B in ADCSELH. Port 2.4 */ #define ADC10B_ 0xBF /* 1 = ADC10B in ADCSELH. Port 2.3 */ #define ADC11B_ 0x7F /* 1 = ADC11B in ADCSELH. Port 2.2 */ /*------------------------------------------------ ADCON (EFh) Bit Value ------------------------------------------------*/ #define ADIV_ 0x04; /* 0 = ADIV in ADCON(EFh) : Fosc/2. (Default) */ /* 1 = ADIV in ADCON : PWM Clock as FADC */ #define AVREF_ 0x80; /* 0 = AVREF in ADCON : Vref using VDD.(Default) */ /* 1 = AVREF in ADCON : Vref using Port 0.3 */ #define ADCF_ 0x10 /* ADC Interrupt Flag. Must be Cleared by S/W */ #define AD_END_ 0x20 /* Current ADC Status. (Read Only) 1 = ADC is END (Default). 0 = ADC is running now */ #define AD_REQ_ 0x40 /* ADC Start Enable. */ /* Clear when AD_END goes to 1 from 0. */ #define AD_EN_ 0x80 /* ADC Ready Enable */ /*------------------------------------------------ ACC Bit Register ------------------------------------------------*/ sbit ACC_0 = 0xE0; sbit ACC_1 = 0xE1; sbit ACC_2 = 0xE2; sbit ACC_3 = 0xE3; sbit ACC_4 = 0xE4; sbit ACC_5 = 0xE5; sbit ACC_6 = 0xE6; sbit ACC_7 = 0xE7; sbit ACC0 = 0xE0; sbit ACC1 = 0xE1; sbit ACC2 = 0xE2; sbit ACC3 = 0xE3; sbit ACC4 = 0xE4; sbit ACC5 = 0xE5; sbit ACC6 = 0xE6; sbit ACC7 = 0xE7; /*------------------------------------------------ EIE Bit Register ------------------------------------------------*/ sbit EX2 = 0xE8; sbit EX3 = 0xE9; sbit EWDT = 0xEC; sbit EPWM = 0xED; /*------------------------------------------------ EIP Bit Register ------------------------------------------------*/ sbit PX2 = 0xF8; sbit PX3 = 0xF9; sbit PWDT = 0xFC; sbit PPWM = 0xFD; /*------------------------------------------------ P0DIR (F4h) Bit Value ------------------------------------------------*/ #define P0DIR7_ 0x80 /* Port0 input/output control */ #define P0DIR6_ 0x40 /* 1 = Input (Default) */ #define P0DIR5_ 0x20 /* 0 = Output */ #define P0DIR4_ 0x10 #define P0DIR3_ 0x08 #define P0DIR2_ 0x04 #define P0DIR1_ 0x02 #define P0DIR0_ 0x01 /*------------------------------------------------ P1DIR (F5h) Bit Value ------------------------------------------------*/ #define P1DIR7_ 0x80 /* Port1 input/output control */ #define P1DIR6_ 0x40 /* 1 = Input (Default) */ #define P1DIR5_ 0x20 /* 0 = Output */ #define P1DIR4_ 0x10 #define P1DIR3_ 0x08 #define P1DIR2_ 0x04 #define P1DIR1_ 0x02 #define P1DIR0_ 0x01 /*------------------------------------------------ P2DIR (F6h) Bit Value ------------------------------------------------*/ #define P2DIR7_ 0x80 /* Port2 input/output control */ #define P2DIR6_ 0x40 /* 1 = Input (Default) */ #define P2DIR5_ 0x20 /* 0 = Output */ #define P2DIR4_ 0x10 #define P2DIR3_ 0x08 #define P2DIR2_ 0x04 #define P2DIR1_ 0x02 #define P2DIR0_ 0x01 /*------------------------------------------------ Interrupt Vectors: Interrupt Address = (Number * 8) + 3 ------------------------------------------------*/ #define IE0_VECTOR 0 /* 0x03 External Interrupt 0 */ #define TF0_VECTOR 1 /* 0x0B Timer 0 */ #define IE1_VECTOR 2 /* 0x13 External Interrupt 1 */ #define TF1_VECTOR 3 /* 0x1B Timer 1 */ #define SIO_VECTOR 4 /* 0x23 Serial Port */ #define ADC_VECTOR 7 /* 0x3B ADC */ #define IE2_VECTOR 8 /* 0x43 External Interrupt 2 */ #define IE3_VECTOR 9 /* 0x4B External Interrupt 3 */ #define I2C_M_VECTOR 10 /* 0x53 I2C Master Interrupt */ #define I2C_S_VECTOR 11 /* 0x5B I2C Slave Interrupt */ #define WDT_VECTOR 12 /* 0x63 Interrupt Watchdog Timer */ #define PWM_VECTOR 13 /* 0x6B Interrupt PWM */ /*------------------------------------------------ Register Banks ------------------------------------------------*/ #define REGISTER_BANK_0 0 /* Register Bank 0 */ #define REGISTER_BANK_1 1 /* Register Bank 1 */ #define REGISTER_BANK_2 2 /* Register Bank 2 */ #define REGISTER_BANK_3 3 /* Register Bank 3 */ /*----------------------------------------------*/ #endif