/*-------------------------------------------------------------------------- MiDAS30.H (Ver 0.1) Header file for the CoreRiver Turbo MiDAS3.0 Series MiDAS3.0-MLF32 : 32 Pins MLF Package Copyright (c) 2006-2007 CoreRiver Semiconductor, Inc. All rights reserved. --------------------------------------------------------------------------*/ #ifndef MiDAS30_HEADER_FILE #define MiDAS30_HEADER_FILE 1 //#ifndef C80C590_HEADER_FILE //#define GC80C590_HEADER_FILE 1 /*------------------------------------------------ Byte Registers ------------------------------------------------*/ sfr P0 = 0x80; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr ADCON = 0x84; sfr ADCSEL = 0x85; sfr ADCR = 0x86; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr CKCON = 0x8E; sfr RINGCON = 0x8F; sfr P1 = 0x90; sfr EXIF = 0x91; sfr C0CAP0L = 0x92; sfr C0CAP1L = 0x93; sfr C0CAP2L = 0x94; sfr C0CAP3L = 0x95; sfr C0CAP4L = 0x96; sfr C0CAP5L = 0x97; sfr SCON = 0x98; sfr SBUF = 0x99; sfr C0CAP0H = 0x9A; sfr C0CAP1H = 0x9B; sfr C0CAP2H = 0x9C; sfr C0CAP3H = 0x9D; sfr C0CAP4H = 0x9E; sfr C0CAP5H = 0x9F; sfr P2 = 0xA0; sfr SBUF1 = 0xA1; sfr C0CAPM0 = 0xA2; sfr C0CAPM1 = 0xA3; sfr C0CAPM2 = 0xA4; sfr C0CAPM3 = 0xA5; sfr C0CAPM4 = 0xA6; sfr C0CAPM5 = 0xA7; sfr IE = 0xA8; sfr SADDR = 0xA9; sfr SADDR1 = 0xAA; sfr SADEN1 = 0xAB; sfr C0CON = 0xAC; sfr C0MOD = 0xAD; sfr C0L = 0xAE; sfr C0H = 0xAF; sfr P3 = 0xB0; sfr SCON1 = 0xB1; sfr IT = 0xB2; sfr P0TYPE = 0xB3; sfr P1TYPE = 0xB4; sfr P2TYPE = 0xB5; sfr P3TYPE = 0xB6; sfr IPH = 0xB7; sfr IP = 0xB8; sfr SADEN = 0xB9; sfr ITSEL = 0xBA; sfr P0DIR = 0xBB; sfr P1DIR = 0xBC; sfr P2DIR = 0xBD; sfr P3DIR = 0xBE; sfr AUXAD = 0xBF; sfr PLLCON = 0xC1; sfr PLLNR = 0xC2; sfr PLLFR = 0xC3; sfr STATUS = 0xC5; sfr OSCICN = 0xC6; sfr IOCFG = 0xC7; sfr T2CON = 0xC8; sfr T2MOD = 0xC9; sfr RCAP2L = 0xCA; sfr RCAP2H = 0xCB; sfr TL2 = 0xCC; sfr TH2 = 0xCD; sfr C1CON = 0xCE; sfr C1MOD = 0xCF; sfr PSW = 0xD0; sfr P0SEL = 0xD1; sfr C1CAP0L = 0xD2; sfr C1CAP1L = 0xD3; sfr C1CAP2L = 0xD4; sfr C1CAP3L = 0xD5; sfr C1CAP4L = 0xD6; sfr C1CAP5L = 0xD7; sfr WDCON = 0xD8; sfr P1SEL = 0xD9; sfr C1CAP0H = 0xDA; sfr C1CAP1H = 0xDB; sfr C1CAP2H = 0xDC; sfr C1CAP3H = 0xDD; sfr C1CAP4H = 0xDE; sfr C1CAP5H = 0xDF; sfr ACC = 0xE0; sfr P2SEL = 0xE1; sfr C1CAPM0 = 0xE2; sfr C1CAPM1 = 0xE3; sfr C1CAPM2 = 0xE4; sfr C1CAPM3 = 0xE5; sfr C1CAPM4 = 0xE6; sfr C1CAPM5 = 0xE7; sfr EIE = 0xE8; sfr P3SEL = 0xE9; sfr C1L = 0xEA; sfr C1H = 0xEB; sfr ADCENB0 = 0xEC; sfr ADCENB1 = 0xED; sfr ADCENB2 = 0xEE; sfr ADCENB3 = 0xEF; sfr B = 0xF0; sfr FAEN = 0xF7; sfr EIP = 0xF8; sfr UINDX = 0xF9; sfr UDATA = 0xFA; sfr CLKSEL = 0xFB; /*------------------------------------------------ P0 Bit Register ------------------------------------------------*/ sbit P0_0 = 0x80; sbit P0_1 = 0x81; sbit P0_2 = 0x82; sbit P0_3 = 0x83; sbit P0_4 = 0x84; sbit P0_5 = 0x85; sbit P0_6 = 0x86; sbit P0_7 = 0x87; sbit P00 = 0x80; sbit P01 = 0x81; sbit P02 = 0x82; sbit P03 = 0x83; sbit P05 = 0x85; sbit P06 = 0x86; sbit P07 = 0x87; sbit C1EX0 = 0x80; sbit C1EX1 = 0x81; sbit C1EX2 = 0x82; sbit C1EX3 = 0x83; sbit C1EX4 = 0x84; sbit C1EX5 = 0x85; sbit ECI1 = 0x86; sbit ECI0 = 0x87; /*------------------------------------------------ PCON Bit Values ------------------------------------------------*/ #define IDL_ 0x01 /* IDLE Mode Bit */ #define PD_ 0x02 /* Power Down Mode Bit */ #define STOP_ 0x02 /* Alterndefinition */ #define GF0_ 0x04 /* General Purpose Flag */ #define GF1_ 0x08 /* General Purpose Flag */ #define POF_ 0x10 /* Power Off Flag */ #define SMOD0_ 0x40 /* When Set, FE Bis Access Enable */ #define SMOD1_ 0x80 /* Timer 1 Baud RDouble in UART Mode 1,2,3. */ /*------------------------------------------------ TCON Bit Register ------------------------------------------------*/ sbit IT0 = 0x88; sbit IE0 = 0x89; sbit IT1 = 0x8A; sbit IE1 = 0x8B; sbit TR0 = 0x8C; sbit TF0 = 0x8D; sbit TR1 = 0x8E; sbit TF1 = 0x8F; /*------------------------------------------------ TMOD Bit Values ------------------------------------------------*/ #define T0_M0_ 0x01 /* T0_M1, T0_M0 : Timer 0 Mode Select. */ #define T0_M1_ 0x02 #define T0_CT_ 0x04 /* Timer 0 Counter/Timer Select. When Set, COunter by T0 pin. */ #define T0_GATE_ 0x08 /* Timer 0 Gate Control */ #define T1_M0_ 0x10 /* T1_M1, T1_M0 : Timer 1 Mode Select. */ #define T1_M1_ 0x20 #define T1_CT_ 0x40 /* Timer 1 Counter/Timer Select. When Set, COunter by T1 pin. */ #define T1_GATE_ 0x80 /* Timer 1 Gate Control */ #define T1_MASK_ 0xF0 #define T0_MASK_ 0x0F /*------------------------------------------------ CKCON Bit Value ------------------------------------------------*/ #define U0T2DIS_ 0x01 /* Used to disable RCLK/TCLK control for UART0 to use T0 overflow for baud rate generation */ #define U1T2DIS_ 0x02 /* Used to disable RCLK/TCLK control for UART1 to use T1 overflow for baud rate generation */ #define T0M_ 0x08 /* Timer 0 Clock Select. When Set, Base Time is 4 Clocks. */ #define T1M_ 0x10 /* Timer 1 Clock Select. When Set, Base Time is 4 Clocks. */ #define T2M_ 0x20 /* Timer 2 Clock Select. When Set, Base Time is 4 Clocks. */ #define WD0_ 0x40 /* Watchdog Timer Mode Select. */ #define WD1_ 0x80 /* [0,0] : 2^17 Clocks(Interrupt), 2^17 + 512 Clocks(Reset). */ /* [0,1] : 2^20 Clocks(Interrupt), 2^20 + 512 Clocks(Reset). */ /* [1,0] : 2^23 Clocks(Interrupt), 2^23 + 512 Clocks(Reset). */ /* [1,1] : 2^26 Clocks(Interrupt), 2^26 + 512 Clocks(Reset). */ /*------------------------------------------------ P1 Bit Register ------------------------------------------------*/ sbit P1_0 = 0x90; sbit P1_1 = 0x91; sbit P1_2 = 0x92; sbit P1_3 = 0x93; sbit P1_4 = 0x94; sbit P1_5 = 0x95; sbit P1_6 = 0x96; sbit P1_7 = 0x97; sbit P10 = 0x90; sbit P11 = 0x91; sbit P12 = 0x92; sbit P13 = 0x93; sbit P14 = 0x94; sbit P15 = 0x95; sbit P16 = 0x96; sbit P17 = 0x97; sbit T2 = 0x90; sbit T2EX = 0x91; sbit INT2 = 0x94; sbit INT3 = 0x95; sbit INT4 = 0x96; sbit INT5 = 0x97; sbit ADC10 = 0x90; sbit ADC11 = 0x91; sbit ADC12 = 0x92; sbit ADC13 = 0x93; sbit ADC14 = 0x94; sbit adc15 = 0x95; sbit ADC16 = 0x96; sbit ADC17 = 0x97; /*------------------------------------------------ EXIF Bit Value ------------------------------------------------*/ #define BGS_ 0x01 /* Band-gap Select. When set, LVD will run in power-down mode. */ #define RGSL_ 0x02 /* When wakeup from power down mode in XTAL clock, use RING oscillator as system clock during 65,536 XTAL clocks */ #define RGMD_ 0x04 /* RING mode */ #define XT_ 0x08 /* Crystal Select. Read only*/ #define IE2_ 0x10 /* External Interrupt 2 Flag */ #define IE3_ 0x20 /* External Interrupt 3 Flag_b */ #define IE4_ 0x40 /* External Interrupt 4 Flag */ #define IE5_ 0x80 /* External Interrupt 5 Flag_b */ /*------------------------------------------------ SCON Bit Register ------------------------------------------------*/ sbit RI = 0x98; sbit TI = 0x99; sbit RB8 = 0x9A; sbit TB8 = 0x9B; sbit REN = 0x9C; sbit SM2 = 0x9D; sbit SM1 = 0x9E; sbit SM0 = 0x9F; /*------------------------------------------------ P2 Bit Register ------------------------------------------------*/ sbit P2_0 = 0xA0; sbit P2_1 = 0xA1; sbit P2_2 = 0xA2; sbit P2_3 = 0xA3; sbit P2_4 = 0xA4; sbit P2_5 = 0xA5; sbit P2_6 = 0xA6; sbit P2_7 = 0xA7; sbit P20 = 0xA0; sbit P21 = 0xA1; sbit P22 = 0xA2; sbit P23 = 0xA3; sbit P24 = 0xA4; sbit P25 = 0xA5; sbit P26 = 0xA6; sbit P27 = 0xA7; sbit C0EX0 = 0xA0; sbit C0EX1 = 0xA1; sbit C0EX2 = 0xA2; sbit C0EX3 = 0xA3; sbit C0EX4 = 0xA4; sbit C0EX5 = 0xA5; sbit RXD1 = 0xA6; sbit TXD1 = 0xA7; /*------------------------------------------------ IE Bit Register ------------------------------------------------*/ sbit EX0 = 0xA8; sbit ET0 = 0xA9; sbit EX1 = 0xAA; sbit ET1 = 0xAB; sbit ES = 0xAC; sbit ET2 = 0xAD; sbit EADC = 0xAE; sbit EA = 0xAF; /*------------------------------------------------ C0CON/C1CON Bit Value ------------------------------------------------*/ #define CCF0_ 0x01 /* MODULE0 interrupt flag */ #define CCF1_ 0x02 /* MODULE1 interrupt flag */ #define CCF2_ 0x04 /* MODULE2 interrupt flag */ #define CCF3_ 0x08 /* MODULE3 interrupt flag */ #define CCF4_ 0x10 /* MODULE4 interrupt flag */ #define CCF5_ 0x20 /* MODULE5 interrupt flag */ #define CR_ 0x40 /* PCA counter run control bit */ #define CF_ 0x80 /* PCA counter overflow flag */ /*------------------------------------------------ C0MOD/C1MOD Bit Value ------------------------------------------------*/ #define ECF_ 0x01 /* Enable PCA counter overflow interrupt */ #define CPS0_ 0x02 /* PCA count rate select [0] */ #define CPS1_ 0x04 /* PCA count rate select [1] */ #define CPS2_ 0x08 /* PCA count rate select [2] */ #define CPS3_ 0x10 /* PCA count rate select [3] */ #define PWMDYN_ 0x40 /* PCA counter runs for dynamic PWM */ #define CIDL_ 0x80 /* Counter Idle Control */ /*------------------------------------------------ P3 Bit Register ------------------------------------------------*/ sbit P3_0 = 0xB0; sbit P3_1 = 0xB1; sbit P3_2 = 0xB2; sbit P3_3 = 0xB3; sbit P3_4 = 0xB4; sbit P3_5 = 0xB5; sbit P3_6 = 0xB6; sbit P3_7 = 0xB7; sbit P30 = 0xB0; sbit P31 = 0xB1; sbit P32 = 0xB2; sbit P33 = 0xB3; sbit P34 = 0xB4; sbit P35 = 0xB5; sbit P36 = 0xB6; sbit P37 = 0xB7; sbit RXD = 0xB0; sbit TXD = 0xB1; sbit INT0 = 0xB2; sbit INT1 = 0xB3; sbit T0 = 0xB4; sbit T1 = 0xB5; sbit WR = 0xB6; sbit RD = 0xB7; /*------------------------------------------------ IPH Bit Value ------------------------------------------------*/ #define PX0H_ 0x01 /* External Interrupt 0 Priority High */ #define PT0H_ 0x02 /* Timer 0 Interrupt Priority High */ #define PX1H_ 0x04 /* External Interrupt 1 Priority High */ #define PT1H_ 0x08 /* Timer 1 Interrupt Priority High */ #define PSH_ 0x10 /* Serial Port Interrupt Priority High */ #define PT2H_ 0x20 /* Timer 2 Interrupt Prioirty High */ #define PADCH_ 0x40 /* ADC Interrupt Priority High */ /*------------------------------------------------ IP Bit Register ------------------------------------------------*/ sbit PX0 = 0xB8; sbit PT0 = 0xB9; sbit PX1 = 0xBA; sbit PT1 = 0xBB; sbit PS = 0xBC; sbit PT2 = 0xBD; sbit PADC = 0xBE; /*------------------------------------------------ PMR Bit Value ------------------------------------------------*/ #define WIOE_ 0x01 /* 1 = Wakeup IO Disable */ #define WCLKE_ 0x02 /* 1 = Wakeup CLK Disable */ #define ALEOFF_ 0x04 /* 1 = ALE Toggling Disable */ #define XTOFF_ 0x08 /* 1 = External crystal will be killed */ /*------------------------------------------------ STATUS Bit Value ------------------------------------------------*/ #define XTUP_ 0x10 /* Crystal oscillator warm-up status */ /*------------------------------------------------ OSCICN Bit Value ------------------------------------------------*/ #define DIV0_ 0x01 /* RING oscillator divider */ #define DIV1_ 0x02 /* RING oscillator divider */ #define RINGON_ 0x04 /* Internal RING oscillator is running */ #define DIV2_ 0x08 /* RING oscillator divider */ /*------------------------------------------------ IOCFG Bit Value ------------------------------------------------*/ #define ENAUX_ 0x08 /* Select AUXAD for MOVX with Ri */ /*------------------------------------------------ T2CON Bit Register ------------------------------------------------*/ sbit CP_RL2 = 0xC8; sbit C_T2 = 0xC9; sbit TR2 = 0xCA; sbit EXEN2 = 0xCB; sbit TCLK = 0xCC; sbit RCLK = 0xCD; sbit EXF2 = 0xCE; sbit TF2 = 0xCF; /*------------------------------------------------ T2MOD Bit Value ------------------------------------------------*/ #define DCEN_ 0x01 /* 1 = Timer 2 Down Count Enable */ #define T2OE_ 0x02 /* 1 = Timer 2 Clock Output to P1.0 */ /*------------------------------------------------ PSW Bit Register ------------------------------------------------*/ sbit F1 = 0xD1; sbit OV = 0xD2; sbit RS0 = 0xD3; sbit RS1 = 0xD4; sbit F0 = 0xD5; sbit AC = 0xD6; sbit CY = 0xD7; /*------------------------------------------------ WDCON Bit Register ------------------------------------------------*/ sbit RWT = 0xD8; sbit EWT = 0xD9; sbit WTRF = 0xDA; sbit WDIF = 0xDB; sbit PFI = 0xDC; sbit EPFI = 0xDD; sbit POR = 0xDE; /*------------------------------------------------ ACC Bit Register ------------------------------------------------*/ sbit ACC_0 = 0xE0; sbit ACC_1 = 0xE1; sbit ACC_2 = 0xE2; sbit ACC_3 = 0xE3; sbit ACC_4 = 0xE4; sbit ACC_5 = 0xE5; sbit ACC_6 = 0xE6; sbit ACC_7 = 0xE7; sbit ACC0 = 0xE0; sbit ACC1 = 0xE1; sbit ACC2 = 0xE2; sbit ACC3 = 0xE3; sbit ACC4 = 0xE4; sbit ACC5 = 0xE5; sbit ACC6 = 0xE6; sbit ACC7 = 0xE7; /*------------------------------------------------ EIE Bit Register ------------------------------------------------*/ sbit EX2 = 0xE8; sbit EX3 = 0xE9; sbit EX4 = 0xEA; sbit EX5 = 0xEB; sbit EWDT = 0xEC; sbit ES1 = 0xED; sbit EPCA0 = 0xEE; sbit EPCA1 = 0xEF; /*------------------------------------------------ ADCSEL Bit Value ------------------------------------------------*/ #define ADCS0_ 0x01 /* ADC active channel MUX selection [0] */ #define ADCS1_ 0x02 /* ADC active channel MUX selection [1] */ #define ADCS2_ 0x04 /* ADC active channel MUX selection [2] */ #define ADCS3_ 0x08 /* ADC active channel MUX selection [3] */ #define ADCS4_ 0x10 /* ADC active channel MUX selection [4] */ #define ADVI0_ 0x20 /* ADIV2, ADIV1, ADIV0 : ADC Input Clock Divide */ #define ADVI1_ 0x40 /* [0,0,0] : 2-divide, [0,0,1] : 4-divide, [0,1,0] : 8-divide */ #define ADVI2_ 0x80 /* [0,1,1] : 16-divide, [1,0,0] : 32-divide ,[1,0,1] : 64-divide */ /* [1,1,0] : 128-divide, [1,1,1] : 256-divide */ /*------------------------------------------------ IT Bit Value : (Interrupt Type Selection Register) ------------------------------------------------*/ #define IT2_ 0x01 /* Interrupt2 Type Selection Flag, 0 : Level, 1 : Edge */ #define IT3_ 0x02 /* Interrupt3 Type Selection Flag, 0 : Level, 1 : Edge */ #define IT4_ 0x04 /* Interrupt4 Type Selection Flag, 0 : Level, 1 : Edge */ #define IT5_ 0x08 /* Interrupt5 Type Selection Flag, 0 : Level, 1 : Edge */ #define I2C_EN_ 0x10 /* Normal I2C Enable Flag, 0 : I2C Disable, 1 : Enable */ #define PI2C_ 0x20 /* I2C Interrupt Priorty */ #define FI2C_ 0x40 /* I2C Interrupt Flag */ #define EI2C_ 0x80 /* I2C Interrupt Enable Flag */ /*------------------------------------------------ ITSEL Bit Value 0 : Low Level or Negative Edge Dedect 1 : High Level or Positive Edge Dedect ------------------------------------------------*/ #define ITSEL2_ 0x04 /* Interrupt2 Polarity Selection Flag */ #define ITSEL3_ 0x08 /* Interrupt3 Polarity Selection Flag */ #define ITSEL4_ 0x10 /* Interrupt4 Polarity Selection Flag */ #define ITSEL5_ 0x20 /* Interrupt5 Polarity Selection Flag */ /*------------------------------------------------ PLLCON Bit Value (PLL Control Register) ------------------------------------------------*/ #define PLLBP_ 0x01 /* 1 : PLL Bypass Mode, 0 : PLL Normal Mode */ #define PLLPD_ 0x02 /* 1 : PLL Power Down , 0 : PLL Active */ #define PH_SEL_ 0x04 /* PFD Phase control */ #define DLY_CTR_ 0x08 /* PFD Delay Control */ #define ICP0_ 0x10 /* CP Current Control */ #define ICP1_ 0x20 /* */ #define FOE_ 0x40 /* PLL clock output enable [P1.3] */ #define LOCK_ 0x80 /* 1 : PLL Lock , 0 : PLL Unlock */ /*------------------------------------------------ PLLNR Bit Value (PLL Input Divider Register) ------------------------------------------------*/ #define RDIV0_ 0x01 /* Rdiv[1:0], Input 2-bit divider */ #define RDIV1_ 0x02 /* */ #define ODIV0_ 0x04 /* Odiv[1:0], Output 2-bit divider */ #define ODIV1_ 0x08 /* */ /*------------------------------------------------ UINDX Bit Value (Wakeup / I2C Index Register) ------------------------------------------------*/ #define UINDX0_ 0x01 /* Wakeup Index Register, [0XXXXX] : Wakeup Register */ #define UINDX1_ 0x02 /* [10000] : I2C RX FIFO Read Indirect Address, */ #define UINDX2_ 0x04 /* [10001] : I2C TX FIFO Write Indirect Address, */ #define UINDX3_ 0x08 /* [10010] : I2C RX FIFO Pointer Indirect Address, */ #define UINDX4_ 0x10 /* [10011] : I2C TX FIFO Pointer Indirect Address, */ #define I2C_RXP_ 0x40 /* I2C RX FIFO pop, 0 : IDLE , 1 : Pop FIFO, And move data to UDATA SFR */ #define I2C_BS_ 0x80 /* I2C Busy Flag, 0 : IDLE , 1 : Busy */ /*------------------------------------------------ CLSEL Bit Value (Wakeup / I2C Data Register) ------------------------------------------------*/ #define OSC32EB_ 0x01 /* 32KHz Ring Enable Bar, 0 : 32KHz Enable, 1 : 32KHz Disable */ #define RG_PR_ 0x02 /* Ring Clock Selection */ /* 0 : 32KHz Ring clock for WDT Power Down */ /* 1 : 4MHz Ring clock for Normal Operation */ #define XR_PL_ 0x04 /* PLL Clock / XTRG Clock Selection */ /* 0 : PLL Clock */ /* 1 : XTAL / Ring MUX Clock */ #define WDEM_ 0x08 /* Watchdog timer extension mode select */ #define XR_HF_ 0x10 /* XTAL Division flag, 1 : XTAL/2 Division */ /*------------------------------------------------ ADCON Bit Value ------------------------------------------------*/ #define ADCF_ 0x10 /* ADC Interrupt Flag. Must be Cleared by S/W */ #define AD_END_ 0x20 /* Current ADC Status. 0 = ADC is running now */ #define AD_REQ_ 0x40 /* ADC Start Enable. Clear when AD_END goes to 1 from 0. */ #define AD_EN_ 0x80 /* ADC Ready Enable */ /*------------------------------------------------ EIP Bit Register ------------------------------------------------*/ sbit PX2 = 0xF8; sbit PX3 = 0xF9; sbit PX4 = 0xFA; sbit PX5 = 0xFB; sbit PWDT = 0xFC; sbit PS1 = 0xFD; sbit PPCA0 = 0xFE; sbit PPCA1 = 0xFF; /*------------------------------------------------ Interrupt Vectors: Interrupt Address = (Number * 8) + 3 ------------------------------------------------*/ #define IE0_VECTOR 0 /* 0x03 External Interrupt 0 */ #define TF0_VECTOR 1 /* 0x0B Timer 0 */ #define IE1_VECTOR 2 /* 0x13 External Interrupt 1 */ #define TF1_VECTOR 3 /* 0x1B Timer 1 */ #define SIO_VECTOR 4 /* 0x23 Serial Port */ #define TF2_VECTOR 5 /* 0x2B Timer 2 */ #define ADC_VECTOR 7 /* 0x3B ADC */ #define IE2_VECTOR 8 /* 0x43 External Interrupt 2 */ #define IE3_VECTOR 9 /* 0x4B External Interrupt 3 */ #define IE4_VECTOR 10 /* 0x53 External Interrupt 4 */ #define IE5_VECTOR 11 /* 0x5B External Interrupt 5 */ #define WDT_VECTOR 12 /* 0x63 Interrupt Watchdog Timer */ #define SIO1_VECTOR 13 /* 0x6B Serial Port 1 */ #define PCA0_VECTOR 14 /* 0x73 PCA 0 */ #define PCA1_VECTOR 15 /* 0x7B PCA 1 */ #define I2C_VECTOR 16 /* 0x83 I2C */ /*----------------------------------------------*/ #endif