/*-------------------------------------------------------------------------- GC80C520_PL44I.H (ver 1.0) Header file for the GenCore Turbo GC80C520 Family GC87C520G0-PL44I : 44 Pins PLCC Package GC87C520G0-LQ44I : 44 Pins LQFP Package GC87C520G0-P40I : 40 Pins PDIP Package GC81C520G0-PL44I : 44 Pins PLCC Package GC81C520G0-LQ44I : 44 Pins LQFP Package GC81C520G0-P40I : 40 Pins PDIP Package GC80C520G0-PL44I : 44 Pins PLCC Package GC80C520G0-LQ44I : 44 Pins LQFP Package GC80C520G0-P40I : 40 Pins PDIP Package GC87C520A0-PL44I : 44 Pins PLCC Package GC87C520A0-LQ44I : 44 Pins LQFP Package GC87C520A0-P40I : 40 Pins PDIP Package GC81C520A0-PL44I : 44 Pins PLCC Package GC81C520A0-LQ44I : 44 Pins LQFP Package GC81C520A0-P40I : 40 Pins PDIP Package GC80C520A0-PL44I : 44 Pins PLCC Package GC80C520A0-LQ44I : 44 Pins LQFP Package GC80C520A0-P40I : 40 Pins PDIP Package Copyright (c) 2003-2004 GenCore Technology, Inc. All rights reserved. --------------------------------------------------------------------------*/ #ifndef GC80C520_HEADER_FILE #define GC80C520_HEADER_FILE 1 /*------------------------------------------------ Byte Registers ------------------------------------------------*/ sfr P0 = 0x80; /* Port 0 */ sfr p0 = 0x80; /* Port 0 */ sfr SP = 0x81; /* Stack Pointer */ sfr sp = 0x81; /* Stack Pointer */ sfr DPL = 0x82; /* Data Pointer Low */ sfr dpl = 0x82; /* Data Pointer Low */ sfr DPH = 0x83; /* Data Pointer High */ sfr dph = 0x83; /* Data Pointer High */ sfr DPS = 0x86; /* Data Pointer Select */ sfr dps = 0x86; /* Data Pointer Select */ sfr PCON = 0x87; /* Power Control */ sfr pcon = 0x87; /* Power Control */ sfr TCON = 0x88; /* Timer 0/1 Control */ sfr tcon = 0x88; /* Timer 0/1 Control */ sfr TMOD = 0x89; /* Timer 0/1 Mode Control */ sfr tmod = 0x89; /* Timer 0/1 Mode Control */ sfr TL0 = 0x8A; /* Timer 0 Low Byte */ sfr tl0 = 0x8A; /* Timer 0 Low Byte */ sfr TL1 = 0x8B; /* Timer 1 Low Byte */ sfr tl1 = 0x8B; /* Timer 1 Low Byte */ sfr TH0 = 0x8C; /* Timer 0 High Byte */ sfr th0 = 0x8C; /* Timer 0 High Byte */ sfr TH1 = 0x8D; /* Timer 1 High Byte */ sfr th1 = 0x8D; /* Timer 1 High Byte */ sfr CKCON = 0x8E; /* Clock Control */ sfr ckcon = 0x8E; /* Clock Control */ sfr P1 = 0x90; /* Port 1 */ sfr p1 = 0x90; /* Port 1 */ sfr EXIF = 0x91; /* External Interrupt Flag */ sfr exif = 0x91; /* External Interrupt Flag */ sfr SCON = 0x98; /* Serial Port Control */ sfr scon = 0x98; /* Serial Port Control */ sfr SBUF = 0x99; /* Serial Data Buffer */ sfr sbuf = 0x99; /* Serial Data Buffer */ sfr P2 = 0xA0; /* Port 2 */ sfr p2 = 0xA0; /* Port 2 */ sfr P4 = 0xA5; /* Port 4 */ sfr p4 = 0xA5; /* Port 4 */ sfr P4SEL = 0xA6; /* Port 4 Pull-up Control */ sfr p4sel = 0xA6; /* Port 4 Pull-up Control */ sfr IE = 0xA8; /* Interrupt Enable */ sfr ie = 0xA8; /* Interrupt Enable */ sfr SADDR = 0xA9; /* Slave Address Register */ sfr saddr = 0xA9; /* Slave Address Register */ sfr P3 = 0xB0; /* Port 3 */ sfr p3 = 0xB0; /* Port 3 */ sfr IPH = 0xB7; /* Interrupt Priority High */ sfr iph = 0xB7; /* Interrupt Priority High */ sfr IP = 0xB8; /* Interrupt Priority Low */ sfr ip = 0xB8; /* Interrupt Priority Low */ sfr SADEN = 0xB9; /* Slave Address Mask Enable */ sfr saden = 0xB9; /* Slave Address Mask Enable */ sfr PMR = 0xC4; /* Power Management Control */ sfr pmr = 0xC4; /* Power Management Control */ sfr STATUS = 0xC5; /* Crystal Status */ sfr status = 0xC5; /* Crystal Status */ sfr T2CON = 0xC8; /* Timer 2 Control */ sfr t2con = 0xC8; /* Timer 2 Control */ sfr T2MOD = 0xC9; /* Timer 2 Mode */ sfr t2mod = 0xC9; /* Timer 2 Mode */ sfr RCAP2L = 0xCA; /* Timer 2 Capture/Reload Low Byte */ sfr rcap2l = 0xCA; /* Timer 2 Capture/Reload Low Byte */ sfr RCAP2H = 0xCB; /* Timer 2 Capture/Reload High byte */ sfr rcap2h = 0xCB; /* Timer 2 Capture/Reload High byte */ sfr TL2 = 0xCC; /* Timer 2 Low Byte */ sfr tl2 = 0xCC; /* Timer 2 Low Byte */ sfr TH2 = 0xCD; /* Timer 2 High Byte */ sfr th2 = 0xCD; /* Timer 2 High Byte */ sfr PSW = 0xD0; /* Program Status Word */ sfr psw = 0xD0; /* Program Status Word */ sfr WDCON = 0xD8; /* Watchdog & Power Status */ sfr wdcon = 0xD8; /* Watchdog & Power Status */ sfr PWM0CON = 0xDC; /* PWM 0 Control */ sfr pwm0con = 0xDC; /* PWM 0 Control */ sfr PWM1CON = 0xDD; /* PWM 1 Control */ sfr pwm1con = 0xDD; /* PWM 1 Control */ sfr PWM0D = 0xDE; /* PWM 0 Duty Data */ sfr pwm0d = 0xDE; /* PWM 0 Duty Data */ sfr PWM1D = 0xDF; /* PWM 1 Duty Data */ sfr pwm1d = 0xDF; /* PWM 1 Duty Data */ sfr ACC = 0xE0; /* Accumulator : A Register */ sfr acc = 0xE0; /* Accumulator : A Register */ sfr ADCSEL = 0xE2; /* AD Clock and Port Control */ sfr adcsel = 0xE2; /* AD Clock and Port Control */ sfr ALTSEL = 0xE3; /* Alternative Funcrion Selection */ sfr altsel = 0xE3; /* Alternative Funcrion Selection */ sfr P0SEL = 0xE4; /* Port 0 Pull-up Control */ sfr p0sel = 0xE4; /* Port 0 Pull-up Control */ sfr P1SEL = 0xE5; /* Port 1 Pull-up Control */ sfr p1sel = 0xE5; /* Port 1 Pull-up Control */ sfr P2SEL = 0xE6; /* Port 2 Pull-up Control */ sfr p2sel = 0xE6; /* Port 2 Pull-up Control */ sfr P3SEL = 0xE7; /* Port 3 Pull-up Control */ sfr p3sel = 0xE7; /* Port 3 Pull-up Control */ sfr EIE = 0xE8; /* Extended Interrupy Enable */ sfr eie = 0xE8; /* Extended Interrupy Enable */ sfr ADCR = 0xEE; /* ADC Result Value [8:1] */ sfr adcr = 0xEE; /* ADC Result Value [8:1] */ sfr ADCON = 0xEF; /* ADC Control, ADC Result Value [0] */ sfr adcon = 0xEF; /* ADC Control, ADC Result Value [0] */ sfr B = 0xF0; /* Second Accumulator : B Register */ sfr b = 0xF0; /* Second Accumulator : B Register */ sfr EIP = 0xF8; /* Extended Interrupt Priority */ sfr eip = 0xF8; /* Extended Interrupt Priority */ /*------------------------------------------------ P0 Bit Register ------------------------------------------------*/ sbit P0_0 = 0x80; sbit p0_0 = 0x80; sbit P0_1 = 0x81; sbit p0_1 = 0x81; sbit P0_2 = 0x82; sbit p0_2 = 0x82; sbit P0_3 = 0x83; sbit p0_3 = 0x83; sbit P0_4 = 0x84; sbit p0_4 = 0x84; sbit P0_5 = 0x85; sbit p0_5 = 0x85; sbit P0_6 = 0x86; sbit p0_6 = 0x86; sbit P0_7 = 0x87; sbit p0_7 = 0x87; sbit P00 = 0x80; sbit p00 = 0x80; sbit P01 = 0x81; sbit p01 = 0x81; sbit P02 = 0x82; sbit p02 = 0x82; sbit P03 = 0x83; sbit p03 = 0x83; sbit P04 = 0x84; sbit p04 = 0x84; sbit P05 = 0x85; sbit p05 = 0x85; sbit P06 = 0x86; sbit p06 = 0x86; sbit P07 = 0x87; sbit p07 = 0x87; sbit ADC0 = 0x80; sbit adc0 = 0x80; /*------------------------------------------------ PCON Bit Values ------------------------------------------------*/ #define IDL_ 0x01 /* IDLE Mode Bit */ #define PD_ 0x02 /* Power Down Mode Bit */ #define STOP_ 0x02 /* Alternate definition */ #define GF0_ 0x04 /* General Purpose Flag */ #define GF1_ 0x08 /* General Purpose Flag */ #define POF_ 0x10 /* Power Off Flag */ #define SMOD0_ 0x40 /* When Set, FE Bis Access Enable */ #define SMOD1_ 0x80 /* Timer 1 Baud Rate Double in UART Mode 1,2,3. */ /*------------------------------------------------ TCON Bit Register ------------------------------------------------*/ sbit IT0 = 0x88; /* External Interrupt 0 Type Select */ sbit it0 = 0x88; /* External Interrupt 0 Type Select */ sbit IE0 = 0x89; /* External Interrupt 0 Flag */ sbit ie0 = 0x89; /* External Interrupt 0 Flag */ sbit IT1 = 0x8A; /* External Interrupt 1 Type Select */ sbit it1 = 0x8A; /* External Interrupt 1 Type Select */ sbit IE1 = 0x8B; /* External Interrupt 1 Flag */ sbit ie1 = 0x8B; /* External Interrupt 1 Flag */ sbit TR0 = 0x8C; /* Timer 0 Run Enable */ sbit tr0 = 0x8C; /* Timer 0 Run Enable */ sbit TF0 = 0x8D; /* Timer 0 Overflow Flag */ sbit tf0 = 0x8D; /* Timer 0 Overflow Flag */ sbit TR1 = 0x8E; /* Timer 1 Run Enable */ sbit tr1 = 0x8E; /* Timer 1 Run Enable */ sbit TF1 = 0x8F; /* Timer 1 Overflow Flag */ sbit tf1 = 0x8F; /* Timer 1 Overflow Flag */ /*------------------------------------------------ TMOD Bit Values ------------------------------------------------*/ #define T0_M0_ 0x01 /* T0_M1, T0_M0 : Timer 0 Mode Select. */ #define T0_M1_ 0x02 #define T0_CT_ 0x04 /* Timer 0 Counter/Timer Select. When Set, COunter by T0 pin. */ #define T0_GATE_ 0x08 /* Timer 0 Gate Control */ #define T1_M0_ 0x10 /* T1_M1, T1_M0 : Timer 1 Mode Select. */ #define T1_M1_ 0x20 #define T1_CT_ 0x40 /* Timer 1 Counter/Timer Select. When Set, COunter by T1 pin. */ #define T1_GATE_ 0x80 /* Timer 1 Gate Control */ #define T1_MASK_ 0xF0 #define T0_MASK_ 0x0F /*------------------------------------------------ CKCON Bit Value ------------------------------------------------*/ #define T0M_ 0x08 /* Timer 0 Clock Select. When Set, Base Time is 4 Clocks. */ #define T1M_ 0x10 /* Timer 1 Clock Select. When Set, Base Time is 4 Clocks. */ #define T2M_ 0x20 /* Timer 2 Clock Select. When Set, Base Time is 4 Clocks. */ #define WD0_ 0x40 /* Watchdog Timer Mode Select. */ #define WD1_ 0x80 /* [0,0] : 2^17 Clocks(Interrupt), 2^17 + 512 Clocks(Reset). */ /* [0,1] : 2^20 Clocks(Interrupt), 2^20 + 512 Clocks(Reset). */ /* [1,0] : 2^23 Clocks(Interrupt), 2^23 + 512 Clocks(Reset). */ /* [1,1] : 2^26 Clocks(Interrupt), 2^26 + 512 Clocks(Reset). */ /*------------------------------------------------ P1 Bit Register ------------------------------------------------*/ sbit P1_0 = 0x90; sbit p1_0 = 0x90; sbit P1_1 = 0x91; sbit p1_1 = 0x91; sbit P1_2 = 0x92; sbit p1_2 = 0x92; sbit P1_3 = 0x93; sbit p1_3 = 0x93; sbit P1_4 = 0x94; sbit p1_4 = 0x94; sbit P1_5 = 0x95; sbit p1_5 = 0x95; sbit P1_6 = 0x96; sbit p1_6 = 0x96; sbit P1_7 = 0x97; sbit p1_7 = 0x97; sbit P10 = 0x90; sbit p10 = 0x90; sbit P11 = 0x91; sbit p11 = 0x91; sbit P12 = 0x92; sbit p12 = 0x92; sbit P13 = 0x93; sbit p13 = 0x93; sbit P14 = 0x94; sbit p14 = 0x94; sbit P15 = 0x95; sbit p15 = 0x95; sbit P16 = 0x96; sbit p16 = 0x96; sbit P17 = 0x97; sbit p17 = 0x97; sbit T2 = 0x90; /* External input to Timer/Counter 2, clock out */ sbit t2 = 0x90; /* External input to Timer/Counter 2, clock out */ sbit T2EX = 0x91; /* Timer/Counter 2 capture/reload trigger & dir ctl */ sbit t2ex = 0x91; /* Timer/Counter 2 capture/reload trigger & dir ctl */ sbit INT2 = 0x94; /* External Interrupt 2 */ sbit int2 = 0x94; /* External Interrupt 2 */ sbit INT3 = 0x95; /* External Interrupt 3_b */ sbit int3 = 0x95; /* External Interrupt 3_b */ sbit INT4 = 0x96; /* External Interrupt 4 */ sbit int4 = 0x96; /* External Interrupt 4 */ sbit INT5 = 0x97; /* External Interrupt 5_b */ sbit int5 = 0x97; /* External Interrupt 5_b */ sbit PWM1 = 0x90; /* PWM1 */ sbit pwm1 = 0x90; /* PWM1 */ sbit ADC1 = 0x91; /* ADC1 */ sbit adc1 = 0x91; /* ADC1 */ sbit ADC2 = 0x92; /* ADC2 */ sbit adc2 = 0x92; /* ADC2 */ sbit ADC3 = 0x93; /* ADC3 */ sbit adc3 = 0x93; /* ADC3 */ /*------------------------------------------------ EXIF Bit Value ------------------------------------------------*/ #define BGS_ 0x01 /* Band-gap Select. When set, LVD will run in power-down mode. */ #define XT_ 0x08 /* Crystal Select. Read only*/ #define IE2_ 0x10 /* External Interrupt 2 Flag */ #define IE3_ 0x20 /* External Interrupt 3 Flag_b */ #define IE4_ 0x40 /* External Interrupt 4 Flag */ #define IE5_ 0x80 /* External Interrupt 5 Flag_b */ /*------------------------------------------------ SCON Bit Register ------------------------------------------------*/ sbit RI = 0x98; /* Reception Interrupt Flag */ sbit ri = 0x98; /* Reception Interrupt Flag */ sbit TI = 0x99; /* Transmission Interrupt Flag */ sbit ti = 0x99; /* Transmission Interrupt Flag */ sbit RB8 = 0x9A; /* 9th Bit that was received in Mode 2 & 3 */ sbit rb8 = 0x9A; /* 9th Bit that was received in Mode 2 & 3 */ sbit TB8 = 0x9B; /* 9th Bit that will be transmitted in Mode 2 & 3 */ sbit tb8 = 0x9B; /* 9th Bit that will be transmitted in Mode 2 & 3 */ sbit REN = 0x9C; /* Serial Reception Enable */ sbit ren = 0x9C; /* Serial Reception Enable */ sbit SM2 = 0x9D; /* Enables the Automatic Address Recognition in Mode 2&3 */ sbit sm2 = 0x9D; /* Enables the Automatic Address Recognition in Mode 2&3 */ sbit SM1 = 0x9E; /* SM1, SM0 : Serial Port Mode Select */ sbit sm1 = 0x9E; /* SM1, SM0 : Serial Port Mode Select */ sbit SM0 = 0x9F; /* [0,0] = Mode 0, [0,1] = Mode 1 */ /* [1,0] = Mode 2, [1,1] = Mode 3 */ sbit sm0 = 0x9F; /* [0,0] = Mode 0, [0,1] = Mode 1 */ /* [1,0] = Mode 2, [1,1] = Mode 3 */ /*------------------------------------------------ P2 Bit Register ------------------------------------------------*/ sbit P2_0 = 0xA0; sbit p2_0 = 0xA0; sbit P2_1 = 0xA1; sbit p2_1 = 0xA1; sbit P2_2 = 0xA2; sbit p2_2 = 0xA2; sbit P2_3 = 0xA3; sbit p2_3 = 0xA3; sbit P2_4 = 0xA4; sbit p2_4 = 0xA4; sbit P2_5 = 0xA5; sbit p2_5 = 0xA5; sbit P2_6 = 0xA6; sbit p2_6 = 0xA6; sbit P2_7 = 0xA7; sbit p2_7 = 0xA7; sbit P20 = 0xA0; sbit p20 = 0xA0; sbit P21 = 0xA1; sbit p21 = 0xA1; sbit P22 = 0xA2; sbit p22 = 0xA2; sbit P23 = 0xA3; sbit p23 = 0xA3; sbit P24 = 0xA4; sbit p24 = 0xA4; sbit P25 = 0xA5; sbit p25 = 0xA5; sbit P26 = 0xA6; sbit p26 = 0xA6; sbit P27 = 0xA7; sbit p27 = 0xA7; /*------------------------------------------------ IE Bit Register ------------------------------------------------*/ sbit EX0 = 0xA8; /* 1=Enable External interrupt 0 */ sbit ex0 = 0xA8; /* 1=Enable External interrupt 0 */ sbit ET0 = 0xA9; /* 1=Enable Timer 0 interrupt */ sbit et0 = 0xA9; /* 1=Enable Timer 0 interrupt */ sbit EX1 = 0xAA; /* 1=Enable External interrupt 1 */ sbit ex1 = 0xAA; /* 1=Enable External interrupt 1 */ sbit ET1 = 0xAB; /* 1=Enable Timer 1 interrupt */ sbit et1 = 0xAB; /* 1=Enable Timer 1 interrupt */ sbit ES = 0xAC; /* 1=Enable Serial port interrupt */ sbit es = 0xAC; /* 1=Enable Serial port interrupt */ sbit ET2 = 0xAD; /* 1=Enable Timer 2 interrupt */ sbit et2 = 0xAD; /* 1=Enable Timer 2 interrupt */ sbit EADC = 0xAE; /* ADC Interrupt Enable */ sbit eadc = 0xAE; /* ADC Interrupt Enable */ sbit EA = 0xAF; /* 0=Disable all interrupts */ sbit ea = 0xAF; /* 0=Disable all interrupts */ /*------------------------------------------------ P3 Bit Register ------------------------------------------------*/ sbit P3_0 = 0xB0; sbit p3_0 = 0xB0; sbit P3_1 = 0xB1; sbit p3_1 = 0xB1; sbit P3_2 = 0xB2; sbit p3_2 = 0xB2; sbit P3_3 = 0xB3; sbit p3_3 = 0xB3; sbit P3_4 = 0xB4; sbit p3_4 = 0xB4; sbit P3_5 = 0xB5; sbit p3_5 = 0xB5; sbit P3_6 = 0xB6; sbit p3_6 = 0xB6; sbit P3_7 = 0xB7; sbit p3_7 = 0xB7; sbit P30 = 0xB0; sbit p30 = 0xB0; sbit P31 = 0xB1; sbit p31 = 0xB1; sbit P32 = 0xB2; sbit p32 = 0xB2; sbit P33 = 0xB3; sbit p33 = 0xB3; sbit P34 = 0xB4; sbit p34 = 0xB4; sbit P35 = 0xB5; sbit p35 = 0xB5; sbit P36 = 0xB6; sbit p36 = 0xB6; sbit P37 = 0xB7; sbit p37 = 0xB7; sbit RXD = 0xB0; /* Serial data input */ sbit rxd = 0xB0; /* Serial data input */ sbit TXD = 0xB1; /* Serial data output */ sbit txd = 0xB1; /* Serial data output */ sbit INT0 = 0xB2; /* External interrupt 0_b */ sbit int0 = 0xB2; /* External interrupt 0_b */ sbit INT1 = 0xB3; /* External interrupt 1_b */ sbit int1 = 0xB3; /* External interrupt 1_b */ sbit T0 = 0xB4; /* Timer 0 external input */ sbit t0 = 0xB4; /* Timer 0 external input */ sbit PWM0 = 0xB4; /* PWM0 */ sbit pwm0 = 0xB4; /* PWM0 */ sbit T1 = 0xB5; /* Timer 1 external input */ sbit t1 = 0xB5; /* Timer 1 external input */ sbit WR = 0xB6; /* External data memory write strobe_b */ sbit wr = 0xB6; /* External data memory write strobe_b */ sbit RD = 0xB7; /* External data memory read strobe_b */ sbit rd = 0xB7; /* External data memory read strobe_b */ /*------------------------------------------------ IPH Bit Value ------------------------------------------------*/ #define PX0H_ 0x01 /* External Interrupt 0 Priority High */ #define PT0H_ 0x02 /* Timer 0 Interrupt Priority High */ #define PX1H_ 0x04 /* External Interrupt 1 Priority High */ #define PT1H_ 0x08 /* Timer 1 Interrupt Priority High */ #define PSH_ 0x10 /* Serial Port Interrupt Priority High */ #define PT2H_ 0x20 /* Timer 2 Interrupt Prioirty High */ #define PADCH_ 0x40 /* ADC Interrupt Priority High */ /*------------------------------------------------ IP Bit Register ------------------------------------------------*/ sbit PX0 = 0xB8; /* External Interrupt 0 Priority Low */ sbit px0 = 0xB8; /* External Interrupt 0 Priority Low */ sbit PT0 = 0xB9; /* Timer 0 Interrypt Priority Low */ sbit pt0 = 0xB9; /* Timer 0 Interrypt Priority Low */ sbit PX1 = 0xBA; /* External Interrupy 1 Priority Low */ sbit px1 = 0xBA; /* External Interrupy 1 Priority Low */ sbit PT1 = 0xBB; /* Timer 1 Interrupt Priority Low */ sbit pt1 = 0xBB; /* Timer 1 Interrupt Priority Low */ sbit PS = 0xBC; /* Serial Port Interrupt Priority Low */ sbit ps = 0xBC; /* Serial Port Interrupt Priority Low */ sbit PT2 = 0xBD; /* Timer 2 Interrupy Priority Low */ sbit pt2 = 0xBD; /* Timer 2 Interrupy Priority Low */ sbit PADC = 0xBE; /* ADC Interrupt Priority Low */ sbit padc = 0xBE; /* ADC Interrupt Priority Low */ /*------------------------------------------------ PMR Bit Value ------------------------------------------------*/ #define ALEOFF_ 0x04 /* 1 = ALE Toggling Disable */ /*------------------------------------------------ T2CON Bit Register ------------------------------------------------*/ sbit CP_RL2 = 0xC8; /* 0=Reload, 1=Capture select */ sbit cp_rl2 = 0xC8; /* 0=Reload, 1=Capture select */ sbit C_T2 = 0xC9; /* 0=Timer, 1=Counter */ sbit c_t2 = 0xC9; /* 0=Timer, 1=Counter */ sbit TR2 = 0xCA; /* 0=Stop timer, 1=Start timer */ sbit tr2 = 0xCA; /* 0=Stop timer, 1=Start timer */ sbit EXEN2 = 0xCB; /* Timer 2 external enable */ sbit exen2 = 0xCB; /* Timer 2 external enable */ sbit TCLK = 0xCC; /* 0=Serial clock uses Timer 1 overflow, 1=Timer 2 */ sbit tclk = 0xCC; /* 0=Serial clock uses Timer 1 overflow, 1=Timer 2 */ sbit RCLK = 0xCD; /* 0=Serial clock uses Timer 1 overflow, 1=Timer 2 */ sbit rclk = 0xCD; /* 0=Serial clock uses Timer 1 overflow, 1=Timer 2 */ sbit EXF2 = 0xCE; /* Timer 2 external flag */ sbit exf2 = 0xCE; /* Timer 2 external flag */ sbit TF2 = 0xCF; /* Timer 2 overflow flag */ sbit tf2 = 0xCF; /* Timer 2 overflow flag */ /*------------------------------------------------ T2MOD Bit Value ------------------------------------------------*/ #define DCEN_ 0x01 /* 1 = Timer 2 Down Count Enable */ #define T2OE_ 0x02 /* 1 = Timer 2 Clock Output to P1.0 */ /*------------------------------------------------ PSW Bit Register ------------------------------------------------*/ sbit F1 = 0xD1; /* User Flag 1 */ sbit f1 = 0xD1; /* User Flag 1 */ sbit OV = 0xD2; /* Overflow Flag */ sbit ov = 0xD2; /* Overflow Flag */ sbit RS0 = 0xD3; /* RS1, RS0 : Register Bank Select */ sbit rs0 = 0xD3; /* RS1, RS0 : Register Bank Select */ sbit RS1 = 0xD4; /* [0,0] : Bank 0, [0,1] = Bank 1 */ /* [1,0] : Bank 2, [1,1] = Bank 3 */ sbit rs1 = 0xD4; /* [0,0] : Bank 0, [0,1] = Bank 1 */ /* [1,0] : Bank 2, [1,1] = Bank 3 */ sbit F0 = 0xD5; /* User Flag 0 */ sbit f0 = 0xD5; /* User Flag 0 */ sbit AC = 0xD6; /* Auxiliary Carry Flag */ sbit ac = 0xD6; /* Auxiliary Carry Flag */ sbit CY = 0xD7; /* Carry Flag */ sbit cy = 0xD7; /* Carry Flag */ /*------------------------------------------------ WDCON Bit Register ------------------------------------------------*/ sbit RWT = 0xD8; /* Restart Watchdog Timer */ sbit rwt = 0xD8; /* Restart Watchdog Timer */ sbit EWT = 0xD9; /* Watchdog Timer Reset Enable */ sbit ewt = 0xD9; /* Watchdog Timer Reset Enable */ sbit WTRF = 0xDA; /* Watchdog Timer Reset Flag */ sbit wtrf = 0xDA; /* Watchdog Timer Reset Flag */ sbit WDIF = 0xDB; /* Watchdog Timer Interrupt Flag */ sbit wdif = 0xDB; /* Watchdog Timer Interrupt Flag */ sbit PFI = 0xDC; /* Power-fail Interrupt Flag */ sbit pfi = 0xDC; /* Power-fail Interrupt Flag */ sbit EPFI = 0xDD; /* Enable Power-fail Interrupt */ sbit epfi = 0xDD; /* Enable Power-fail Interrupt */ sbit POR = 0xDE; /* Power-on Reset Flag */ sbit por = 0xDE; /* Power-on Reset Flag */ /*------------------------------------------------ PWM0CON Bit Value ------------------------------------------------*/ #define RUN_P0_ 0x01 /* Counter Start Enable */ #define CLR_P0_ 0x02 /* Counter Reset Enable. Clear by H/W */ #define RL_P0_ 0x04 /* Reload Mode Selection. */ /* 0 = 6-bit, 1 = 8-bit Overflow Reload */ #define MODE_P0_ 0x08 /* 8 bits / (2+6) bits Counter Mode Selection */ #define PS0_P0_ 0x10 /* PS2_P0, PS1_P0, PS0_P0 : Prescaled Clock Selection */ #define PS1_P0_ 0x20 /* Fosc / 1,2,4,8,16,32,64,128 Divide */ #define PS2_P0_ 0x40 #define P0SEL_ 0x80 /* PWM 0 Waveform Output to Port 3.4 */ /*------------------------------------------------ PWM1CON Bit Value ------------------------------------------------*/ #define RUN_P1_ 0x01 /* Counter Start Enable */ #define CLR_P1_ 0x02 /* Counter Reset Enable. Clear by H/W */ #define RL_P1_ 0x04 /* Reload Mode Selection. */ /* 0 = 6-bit, 1 = 8-bit Overflow Reload */ #define MODE_P1_ 0x08 /* 8 bits / (2+6) bits Counter Mode Selection */ #define PS0_P1_ 0x10 /* PS2_P1, PS1_P1, PS0_P1 : Prescaled Clock Selection */ #define PS1_P1_ 0x20 /* Fosc / 1,2,4,8,16,32,64,128 Divide */ #define PS2_P1_ 0x40 #define P1SEL_ 0x80 /* PWM 1 Waveform Output to Port 3.4 */ /*------------------------------------------------ ADCSEL Bit Value ------------------------------------------------*/ #define ADC0_ 0x01 /* 1 = ADC0 Analog Input Selection in Port 0.0 */ #define ADC1_ 0x02 /* 1 = ADC1 Analog Input Selection in Port 1.1 */ #define ADC2_ 0x04 /* 1 = ADC2 Analog Input Selection in Port 1.2 */ #define ADC3_ 0x08 /* 1 = ADC3 Analog Input Selection in Port 1.3 */ #define ADIV0_ 0x20 /* ADIV2, ADIV1, ADIV0 : ADC Input Clock Divide */ #define ADIV1_ 0x40 /* [0,0,0] : 1-divide, [0,0,1] : 2-divide, [0,1,0] : 4-divide */ #define ADIV2_ 0x80 /* [0,1,1] : 8-divide, [1,0,0] : 16-divide */ /*------------------------------------------------ EIE Bit Register ------------------------------------------------*/ sbit EX2 = 0xE8; /* External 2 Interrupt Enable */ sbit ex2 = 0xE8; /* External 2 Interrupt Enable */ sbit EX3 = 0xE9; /* External 3 Interrupt Enable */ sbit ex3 = 0xE9; /* External 3 Interrupt Enable */ sbit EX4 = 0xEA; /* External 4 Interrupt Enable */ sbit ex4 = 0xEA; /* External 4 Interrupt Enable */ sbit EX5 = 0xEB; /* External 5 Interrupt Enable */ sbit ex5 = 0xEB; /* External 5 Interrupt Enable */ sbit EWDT = 0xEC; /* Watchdog Interrupt Enable */ sbit ewdt = 0xEC; /* Watchdog Interrupt Enable */ sbit EPWM0 = 0xED; /* PWM 0 Interrupt Enable */ sbit epwm0 = 0xED; /* PWM 0 Interrupt Enable */ sbit EPWM1 = 0xEE; /* PWM 1 Interrupt Enable */ sbit epwm1 = 0xEE; /* PWM 1 Interrupt Enable */ /*------------------------------------------------ ADCON Bit Value ------------------------------------------------*/ #define ACH0_ 0x04 /* ACH1, ACH0 : ADC Channel Selection */ #define ACH1_ 0x08 /* [0,0]=ADC0(P0.0) Input Selection */ /* [0,1]=ADC1(P1.1), [1,0]=ADC2(P1.2), [1,1]=ADC3(P1.3) */ #define ADCF_ 0x10 /* ADC Interrupt Flag. Must be Cleared by S/W */ #define AD_END_ 0x20 /* Current ADC Status. 0 = ADC is running now */ #define AD_REQ_ 0x40 /* ADC Start Enable. Clear when AD_END goes to 1 from 0. */ #define AD_EN_ 0x80 /* ADC Ready Enable */ /*------------------------------------------------ EIP Bit Register ------------------------------------------------*/ sbit PX2 = 0xF8; /* External 2 Interrupt Priority Bit */ sbit px2 = 0xF8; /* External 2 Interrupt Priority Bit */ sbit PX3 = 0xF9; /* External 3 Interrupt Priority Bit */ sbit px3 = 0xF9; /* External 3 Interrupt Priority Bit */ sbit PX4 = 0xFA; /* External 4 Interrupt Priority Bit */ sbit px4 = 0xFA; /* External 4 Interrupt Priority Bit */ sbit PX5 = 0xFB; /* External 5 Interrupt Priority Bit */ sbit px5 = 0xFB; /* External 5 Interrupt Priority Bit */ sbit PWDT = 0xFC; /* Watchdog Interrupt Priority Bit */ sbit pwdt = 0xFC; /* Watchdog Interrupt Priority Bit */ sbit PPWM0 = 0xFD; /* PWM 0 Interrupt Priority Bit */ sbit ppwm0 = 0xFD; /* PWM 0 Interrupt Priority Bit */ sbit PPWM1 = 0xFE; /* PWM 1 Interrupt Priority Bit */ sbit ppwm1 = 0xFE; /* PWM 1 Interrupt Priority Bit */ /*------------------------------------------------ ACC Bit Register ------------------------------------------------*/ sbit ACC_0 = 0xE0; sbit acc_0 = 0xE0; sbit ACC_1 = 0xE1; sbit acc_1 = 0xE1; sbit ACC_2 = 0xE2; sbit acc_2 = 0xE2; sbit ACC_3 = 0xE3; sbit acc_3 = 0xE3; sbit ACC_4 = 0xE4; sbit acc_4 = 0xE4; sbit ACC_5 = 0xE5; sbit acc_5 = 0xE5; sbit ACC_6 = 0xE6; sbit acc_6 = 0xE6; sbit ACC_7 = 0xE7; sbit acc_7 = 0xE7; sbit ACC0 = 0xE0; sbit acc0 = 0xE0; sbit ACC1 = 0xE1; sbit acc1 = 0xE1; sbit ACC2 = 0xE2; sbit acc2 = 0xE2; sbit ACC3 = 0xE3; sbit acc3 = 0xE3; sbit ACC4 = 0xE4; sbit acc4 = 0xE4; sbit ACC5 = 0xE5; sbit acc5 = 0xE5; sbit ACC6 = 0xE6; sbit acc6 = 0xE6; sbit ACC7 = 0xE7; sbit acc7 = 0xE7; /*------------------------------------------------ Interrupt Vectors: Interrupt Address = (Number * 8) + 3 ------------------------------------------------*/ #define IE0_VECTOR 0 /* 0x03 External Interrupt 0 */ #define TF0_VECTOR 1 /* 0x0B Timer 0 */ #define IE1_VECTOR 2 /* 0x13 External Interrupt 1 */ #define TF1_VECTOR 3 /* 0x1B Timer 1 */ #define SIO_VECTOR 4 /* 0x23 Serial Port */ #define TF2_VECTOR 5 /* 0x2B Timer 2 */ #define ADC_VECTOR 7 /* 0x3B ADC */ #define IE2_VECTOR 8 /* 0x43 External Interrupt 2 */ #define IE3_VECTOR 9 /* 0x4B External Interrupt 3 */ #define IE4_VECTOR 10 /* 0x53 External Interrupt 4 */ #define IE5_VECTOR 11 /* 0x5B External Interrupt 5 */ #define WDT_VECTOR 12 /* 0x63 Interrupt Watchdog Timer */ /*----------------------------------------------*/ #endif