CORERIVER IPs

A. MCU

IP	Spec.	Soft/Hard	Technology	Silicon Proven
MCU	- 8-bit turbo 80C52 architecture - 4 cycles/1 machine cycle - Instruction level compatible with Intel 80C52	Soft	MegnaChip/SEC/ HH-NEC/TSMC	O

B. Memory

IP	Spec.	Soft/Hard	Technology	Silicon Proven
RAM	- 128bytes	Hard(2P3M)	MegnaChip 0.5㎛	O

C. Analog

IP	Spec.	Soft/Hard	Technology	Silicon Proven
ADC	- 10bit, 100Ksps @ 10MHz & 5V	Hard (2P3M)	MegnaChip 0.5㎛	O
	- 10bit, 100Ksps @ 10MHz & 3.3V	Hard (1P3M)	HH-NEC 0.35㎛	O
	- 10bit, 100Ksps @ 10MHz & 3.3V	Hard (1P3M)	TSMC 0.18㎛	O
POR (Power on Reset)	- Level detection type - 1.8V ~ 2.7V	Hard (2P3M)	MegnaChip 0.5㎛	O
	- Level detection type	Hard (1P2M)	HH-NEC 0.35㎛	O
	- Level detection type	Hard (1P2M(	TSMC 0.18㎛	O
LVD (Low Voltage Detector)	- Hysteresis characteristics - 0.2V step detection	Hard (2P3M)	MegnaChip 0.5㎛	O
	- Hysteresis characteristics - 0.2V step detection	Hard (1P2M)	HH-NEC 0.35㎛	O
	- Hysteresis characteristics	Hard (1P2M)	TSMC 0.18㎛	O
RING OSC.	- 4MHz @ 5V (±15%)	Hard (2P3M)	Magna chip 0.5㎛	O
RING OSC.	- 12MHz @ 1.8V	Hard (1P2M)	TSMC 0.18㎛	O
Low Power OSC.	- very low power consumption - Scores of Frequency - Level detecrion type	Hard (1P3M)	HH-NEC 0.35㎛	O
PLL	- Output Frequency : 300MHz ~ 500MHz	Hard (1P3M)	HH-NEC 0.35㎛	O
RF Core	- Output Power : ~ 5dBm - FSK carrier deviation : ~ 100KHz	Hard (1P4M)	HH-NEC 0.35㎛	O

D. I/O

IP	Spec.	Soft/Hard	Technology	Silicon Proven
A/D PAD	- Shared analog & Digtal PAD - One PAD, Two function	Hard (2P3M)	MegnaChip 0.5㎛	O
		Hard (1P4M)	HH-NEC 0.35㎛	O
		Hard (1P4M)	TSMC 0.18㎛	O
I/O	- ESD, Latch-up	Hard (2P3M)	MegnaChip 0.5㎛	O